`include "define.svh"

module hilo_reg(
input wire						clk,
input wire						rst,
//write
input wire							whienable_i,
input wire							wloenable_i,
input wire [`REG_WIDTH - 1 : 0]		whidata_i,
input wire [`REG_WIDTH - 1 : 0]		wlodata_i,
//read
output reg [`REG_WIDTH - 1 : 0]		rhidata_o,
output reg [`REG_WIDTH - 1 : 0]		rlodata_o
    );
    
    reg [`REG_WIDTH - 1 : 0]	hi_reg;
    reg [`REG_WIDTH - 1 : 0]	lo_reg;
    
    always_ff @(posedge clk) begin
    	if (rst == `reset) begin
    		hi_reg <= `ZERO_REG;
    		lo_reg <= `ZERO_REG;
    	end //else
    	else begin
    		if (whienable_i == `true)	hi_reg <= whidata_i;
    		if (wloenable_i == `true)	lo_reg <= wlodata_i;
    	end //else
    end //always
    
    always_comb begin
    	rhidata_o = hi_reg;
    	rlodata_o = lo_reg;
    end //always
    
endmodule
